From f501e0cbd912f78cfcc00d13444a0c32f1e8e6f9 Mon Sep 17 00:00:00 2001
From: Carsten Keller <mail@carstenkeller.dev>
Date: Sun, 9 Jun 2024 17:57:45 +0200
Subject: [PATCH] =?UTF-8?q?Initialisierung=20ge=C3=A4ndert,=20damit=20Offs?=
 =?UTF-8?q?et=20in=20den=20Daten=20verschwindet?=
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---
 Source/ADC.cpp | 50 ++++++++++++++++++++++++++++++--------------------
 Source/ADC.hpp |  4 ++++
 2 files changed, 34 insertions(+), 20 deletions(-)

diff --git a/Source/ADC.cpp b/Source/ADC.cpp
index 14dcbc1..a7e6167 100644
--- a/Source/ADC.cpp
+++ b/Source/ADC.cpp
@@ -74,6 +74,25 @@ namespace ElektronischeLast
     GPIO_InitStruct.Pin = LL_GPIO_PIN_1;
     LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
+    /* Enable ADC internal voltage regulator */
+    LL_ADC_EnableInternalRegulator(ADC1);
+    /* Delay for ADC internal voltage regulator stabilization. */
+    /* Compute number of CPU cycles to wait for, from delay in us. */
+    /* Note: Variable divided by 2 to compensate partially */
+    /* CPU processing cycles (depends on compilation optimization). */
+    /* Note: If system core clock frequency is below 200kHz, wait time */
+    /* is only a few CPU processing cycles. */
+    uint32_t wait_loop_index;
+    wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (100000 * 2))) / 10);
+    while(wait_loop_index != 0)
+    {
+      wait_loop_index--;
+    }
+    LL_ADC_StartCalibration(ADC1);
+    while(LL_ADC_IsCalibrationOnGoing(ADC1))
+    {
+    }
+
     LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_ADC1);
     LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_1, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
     LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PRIORITY_HIGH);
@@ -133,21 +152,6 @@ namespace ElektronischeLast
     LL_ADC_REG_SetTriggerEdge(ADC1, LL_ADC_REG_TRIG_EXT_RISING);
     LL_ADC_SetSamplingTimeCommonChannels(ADC1, LL_ADC_SAMPLINGTIME_COMMON_1, LL_ADC_SAMPLINGTIME_12CYCLES_5);
 
-    /* Enable ADC internal voltage regulator */
-    LL_ADC_EnableInternalRegulator(ADC1);
-    /* Delay for ADC internal voltage regulator stabilization. */
-    /* Compute number of CPU cycles to wait for, from delay in us. */
-    /* Note: Variable divided by 2 to compensate partially */
-    /* CPU processing cycles (depends on compilation optimization). */
-    /* Note: If system core clock frequency is below 200kHz, wait time */
-    /* is only a few CPU processing cycles. */
-    uint32_t wait_loop_index;
-    wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (100000 * 2))) / 10);
-    while(wait_loop_index != 0)
-    {
-      wait_loop_index--;
-    }
-
     /** Configure Regular Channel
     */
     LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_0);
@@ -169,7 +173,7 @@ namespace ElektronischeLast
     {
       .Prescaler = 32,
       .CounterMode = LL_TIM_COUNTERMODE_UP,
-      .Autoreload = 490,
+      .Autoreload = 386,
       .ClockDivision = LL_TIM_CLOCKDIVISION_DIV1,
       .RepetitionCounter = 0,
     };
@@ -180,10 +184,6 @@ namespace ElektronischeLast
     LL_TIM_SetTriggerOutput2(TIM1, LL_TIM_TRGO2_UPDATE);
     LL_TIM_DisableMasterSlaveMode(TIM1);
 
-    LL_ADC_StartCalibration(ADC1);
-    while(LL_ADC_IsCalibrationOnGoing(ADC1))
-    {
-    }
     LL_ADC_Enable(ADC1);
     LL_ADC_REG_StartConversion(ADC1);
     LL_TIM_EnableCounter(TIM1);
@@ -196,4 +196,14 @@ namespace ElektronischeLast
   {
 
   }
+
+  std::uint32_t iADC::get_current(void)
+  {
+
+  }
+
+  std::uint32_t iADC::get_temperature(void)
+  {
+
+  }
 }
diff --git a/Source/ADC.hpp b/Source/ADC.hpp
index cebef30..bf1d5c3 100644
--- a/Source/ADC.hpp
+++ b/Source/ADC.hpp
@@ -8,6 +8,8 @@
 #ifndef ADC_HPP_
 #define ADC_HPP_
 
+#include <cstdint>
+
 namespace ElektronischeLast
 {
   class iADC
@@ -15,6 +17,8 @@ namespace ElektronischeLast
     public:
       iADC(void);
       ~iADC(void);
+      std::uint32_t get_current(void);
+      std::uint32_t get_temperature(void);
     private:
   };
 }